Improved Selection of Test SubSequences in Sequential Circuits for Reduced Power Consumption
نویسندگان
چکیده
A method for the reduction of power dissipation during testing of sequential circuits is presented. In this algorithm from an initial set of test sequences a set of subsequences is properly selected with the purpose of reducing the power consumption without reducing the initial fault coverage. The selection process is accelerated by exploiting the presence of essential sequences and enhanced by introducing to the original test set new GA-engineered test sequences in order to further reduce power consumption. The algorithm as a secondary objective tries to compact the resulting subsequences. Experimental results support the usefulness of the proposed method. Key-Words: Sequential Digital Circuits, Low Power Consumption, Sequence Compaction, Test Generation, Genetic Algorithms.
منابع مشابه
Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)
This study presents the importance of reversible logic in designing of high performance and low power consumption digital circuits. In our research, the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops are investigated based on carbon nanotube field-effect transistors. All reversible flip-flops are simulated in two voltages, 0.3 and 0.5 Volt. Our results show t...
متن کاملLow Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)
Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...
متن کاملReducing Power Consumption during Testing of VLSI Circuits by Proper Subsequence Selection and Modification
A method for minimizing power dissipation in CMOS sequential circuits during test application is presented. Initially, the set of test sequences with the transition counts corresponding to each detected fault is mapped on a Transition Covering Matrix. On this matrix three reduction techniques are applied in cycles in order to reduce the size of the selection problem and thus speed-up the subseq...
متن کاملDesign and Test of New Robust QCA Sequential Circuits
One of the several promising new technologies for computing at nano-scale is quantum-dot cellular automata (QCA). In this paper, new designs for different QCA sequential circuits are presented. Using an efficient QCA D flip-flop (DFF) architecture, a 5-bit counter, a novel single edge generator (SEG) and a divide-by-2 counter are implemented. Also, some types of oscillators, a new edge-t...
متن کاملDesign of low power random number generators for quantum-dot cellular automata
Quantum-dot cellular automata (QCA) are a promising nanotechnology to implement digital circuits at the nanoscale. Devices based on QCA have the advantages of faster speed, lower power consumption, and greatly reduced sizes. In this paper, we are presented the circuits, which generate random numbers in QCA. Random numbers have many uses in science, art, statistics, cryptography, gaming, gambli...
متن کامل